LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; USE IEEE.std_logic_arith.ALL; ENTITY BCDCounter IS PORT( CLK : IN std_logic; QA : out std_logic; QB : out std_logic; QC : out std_logic; QD : out std_logic ); END BCDCounter; ARCHITECTURE rtl of BCDCounter IS SIGNAL counter : std_logic_vector(3 downto 0); BEGIN PROCESS(CLK) BEGIN if(CLK'event and CLK='1') then if( counter = 9 ) then counter <= CONV_STD_LOGIC_VECTOR(0,4); else counter <= counter + 1; end if; end if; END PROCESS; QA <= counter(0); QB <= counter(1); QC <= counter(2); QD <= counter(3); end rtl;