// Converted from ButtonCount.vhd // by VHDL2Verilog ver1.00(2004/05/06) Copyright(c) S.Morioka (http://www02.so-net.ne.jp/~morioka/v2v.htm) // Copyright (C) 1991-2007 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Altera Program License // Subscription Agreement, Altera MegaCore Function License // Agreement, or other applicable license agreement, including, // without limitation, that your use is for the sole purpose of // programming logic devices manufactured by Altera and sold by // Altera or its authorized distributors. Please refer to the // applicable agreement for further details. // PROGRAM "Quartus II" // VERSION "Version 7.1 Build 156 04/30/2007 SJ Web Edition" module ButtonCount(BUTTON, LED_A, LED_B, LED_C, LED_D, LED_E, LED_F, LED_G); input BUTTON; output LED_A; output LED_B; output LED_C; output LED_D; output LED_E; output LED_F; output LED_G; wire SYNTHESIZED_WIRE_0; wire SYNTHESIZED_WIRE_1; wire SYNTHESIZED_WIRE_2; wire SYNTHESIZED_WIRE_3; BCDCounter b2v_inst ( .CLK(BUTTON), .QA(SYNTHESIZED_WIRE_0), .QB(SYNTHESIZED_WIRE_1), .QC(SYNTHESIZED_WIRE_2), .QD(SYNTHESIZED_WIRE_3) ); Decode7Segment b2v_inst1 ( .A(SYNTHESIZED_WIRE_0), .B(SYNTHESIZED_WIRE_1), .C(SYNTHESIZED_WIRE_2), .D(SYNTHESIZED_WIRE_3), .LED_A(LED_A), .LED_B(LED_B), .LED_C(LED_C), .LED_D(LED_D), .LED_E(LED_E), .LED_F(LED_F), .LED_G(LED_G) ); endmodule